1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to methods of manufacture of mask ROM devices and the devices produced thereby.
2. Description of Related Art
The manufacturing process turn around time for manufacture of conventional Mask ROM devices comprises on the order of several weeks. Poor yield prediction is always a problem that exists between the customer and the fabrication operators. On the other hand, the post-metal mask process can provide a short turn around time of a few days. However, the minimum dimension is limited by the ROM photolithographic resolution induced by the metal step height. The cell leakage is also a problem for the post metal ROM.
FIGS. 1A-1F show the process flow for producing a prior art conventional mask ROM device 20.
FIG. 1A shows a first phase of the process performed in manufacturing the device 20 which includes a P- doped silicon substrate 21 with buried N+ bit lines 24. Over the substrate is formed a conventional blanket gate oxide layer 22 upon which is formed a polysilicon word line 23. Over the polysilicon word line 23 is a ROM code implant photoresist mask 25 with an array of openings 19 into which code implant boron B.sup.11 ions 26 are implanted in regions 27 between the buried N+ bit lines 24. After the code has been implanted, the prior art adds the code number process including a first step of forming a photoresist coating; second, exposing the number window; third, code etching; fourth, removing all photoresist.
As shown in FIG. 1B, above the polysilicon word line 23 is formed a blanket dielectric layer 28 of BPSG glass (BPSG (BoroPhosphoSiltcate Glass)) which is a dielectric material that can be used as insulation between semiconductor device structures having a thickness of about 5,500 .ANG. in which a contact hole opening 30 down to word line 23 has been formed by etching through a photoresist mask layer 29.
Then the photoresist mask layer 29 is removed.
Next, as shown in FIG. 1C, a blanket layer of titanium (Ti) 32 is sputtered onto device 20 covering the BPSG layer 28 and the exposed surface of word line 23. Next, the titanium is converted to titanium nitride (TiN) by the process of RTA (rapid thermal annealing.) The process is, first, heat to 600.degree. C. for 60 seconds and second heat to 780.degree. C. for 20-30 seconds with a source of NH.sub.3 +N.sub.2 extending down into contact with polysilicon layer 23 through opening 30 in dielectric layer 28.
Next, as shown in FIG. 1D, the device 20 is coated with a blanket layer of metal 34 (aluminum) with a thickness of 10 k.ANG. formed at a temperature of 400.degree. C. by sputtering for 12 seconds, which extends into opening 30 in electrical contact with the polysilicon layer 23 through the titanium nitride (TiN) layer 32.
Referring to FIG. 1E, the blanket layer of metal 34 on device 20 has been patterned with photolithographic metallization mask with patterns 36 and 37 that were formed above layers 34 and 32 in FIG. 1D. Then an etching process is performed in which mask patterns 36 and 37 are used to protect metal structures 34', 34", 32', 32" which are formed by etching of metal layer 34 and TiN layer 32.
FIG. 1F shows the prior art device of FIG. 1E after the masks 36 and 37 have been removed.
After this stage of the process, the device is passivated in accordance with the state of the art.
FIGS. 5A-5C shows the process flow for producing another prior art conventional mask ROM device 20. FIG. 5A shows the first step performed upon a P- doped silicon substrate 21 with buried N+ bit lines 24. Upon the substrate is a conventional blanket gate oxide layer 22 upon which is formed a blanket polysilicon layer 23 or word line 23.
As shown in FIG. 5B above the polysilicon layer 23 is formed a blanket dielectric layer 28 of BPSG glass having a thickness of about 3,000 .ANG. in which a contact hole opening 30 has been formed into which a blanket layer of titanium (Ti) 32 is sputtered. Next, the titanium is converted to titanium nitride (TiN) by the process of RTA (rapid thermal annealing.) The process is, first, heat to 600.degree. C. for 60 seconds and second heat to 780.degree. C. for 20-30 seconds with a source of NH.sub.3 +N.sub.2 extending down into contact with polysilicon layer through opening 30 in dielectric layer 28.
Next, the device 20 was coated with a blanket layer of metal 34 (aluminum) with a thickness of 10 k.ANG. formed at a temperature of 400.degree. C. by sputtering for 12 seconds, which extends into opening 30 in electrical contact with the polysilicon layer 23 through the titanium nitride (TiN) layer 32. The blanket layer of metal 34 on device 20 was patterned with metallization photolithographic mask with patterns 36 and 37. Mask patterns 36 and 37 are used to protect metal structures 34' and 34" and TiN structures 32' and 32" which are formed by etching of metal layer 34 and TiN layer 32.
Then a ROM code implant photoresist mask 65' is formed over structure 34' with a code ion implant of boron B.sup.11 ions 65 implanted in region 65" between a pair of buried N+ bit lines 24. After the code has been implanted and the prior art adds the code number process including code etching (in post-metal process, one can directly etch without another photoresist step because there is the BPSG layer as the buffer for the cell opening.)
FIG. 5C shows a perspective view of a TiN layer 32 above which is formed an aluminum layer 34.